mwait-idle: update support for Silvermont Core in Baytrail SOC

mwait-idle: update support for Silvermont Core in Baytrail SOC

On some Silvermont-Core/Baytrail-SOC systems,
C1E latency is higher than original specifications.
Although C1E is still enumerated in CPUID.MWAIT.EDX,
we delete the state from intel_idle to avoid latency impact.

Under some conditions, the latency of the C6N-BYT and C6S-BYT states
may exceed the specified values of 40 and 140 usec, respectively.
Increase those values to 300 and 500 usec; to assure
that the hardware does not violate constraints that may be set
by the Linux PM_QOS sub-system.

Also increase the C7-BYT target residency to 4.0 ms from 1.5 ms.

Signed-off-by: Len Brown <len.brown@intel.com>
[Linux commit d7ef76717322c8e2df7d4360b33faa9466cb1a0d]
Signed-off-by: Jan Beulich <jbeulich@suse.com>